This invention relates to a method of producing a Josephson tunnel barrier and more particularly to improvements therein which increase pattern accuracy and eliminate an edge step in a multi-layered film.
In forming a logic circuit or a memory circuit using Josephson junctions, it is necessary to reduce the variance of the critical current values, that is, the maximum current values flowing in tunnel junctions under the zero-voltage state. The critical current value varies with the area of the tunnel junction (barrier), its thickness and its physical properties. As the device size has been reduced and its density has been increased in recent years, a technique of improving the pattern accuracy of the area of the tunnel barrier has become particularly important.
A tunnel-barrier type Josephson junction device consists of a multi-layered film deposited by an evaporation or sputtering process. A method of producing such a device is described in detail, for example, in the article entitled "Fabrication Process for Josephson Integrated Circuits" by J. H. Greiner et al, IBM Journal of Research and Development, Vol. 24, No. 2, pages 195-205, March, 1980. This article reports that when a logic circuit or a memory circuit is fabricated, the multi-layered film formed on the substrate has approximately 14 layers and a total thickness of at least 3 .mu.m. Techniques for eliminating edge step in the multi-layered film are, therefore, of great importance. Unless edge step is eliminated, step coverage would become insufficient at the pattern edge portion, causing deficiencies in various device characteristics, such as a discontinuity in the superconducting electrode and the creation of a short-circuit between the superconducting electrodes despite the interposed insulating layer. Specifically, in comparison with other devices such as semiconductor devices, the Josephson junction device has an extremely small power disipation and hence, a three-dimensional structure device has been proposed in which a plurality of Josephson junction devices are arranged in a direction perpendicular to the substrate. Such a three-dimensional device can not be fabricated readily without edge step elimination techniques.
The following three methods are known in the prior art for fabricating the Josephson integrated circuits, and the following description will be primarily directed to methods of producing the Josephson tunnel-barrier.
In accordance with a first method, a first superconducting electrode consisting of niobium (Nb), lead (Pb) or the like is deposited on an insulating surface of a substrate by an evaporation or sputtering technique and a patterning process is then effected by selectively etching the deposited film using conventional photoresist steps or by a selective lift-off process. Next, an undercut, umbrella-like photoresist mask is formed on the portion of the first superconducting electrode where a tunnel-barrier is to be eventually formed, by soaking in an organic solvent such as chlorobenzene or bromobenzene before or after exposure in the conventional photoresist processing steps. Then, an insulating layer such as silicon monoxide SiO and silicon dioxide SiO.sub.2 is deposited on the surface of the substrate by a film-forming technique with a high directivity, such as an evaporation technique, and a lift-off of the undercut photoresist with the insulating layer thereon is then carried out. The lift-off portion where the insulating layer is removed is oxidized by thermal oxidization or plasma-oxidization to provide a tunnel barrier having a thickness of several tens of angstroms. Thereafter, a second superconducting electrode is formed by depositing a Nb or Pb film and patterning it in the same way as the first superconducting electrode.
This method requires the formation of the undercut, umbrella-like photoresist mask and this undercut quantity is very sensitive to the pre-baking condition of the photoresist, the liquid temperature of the organic solvent and the soaking time. Accordingly, it is extremely difficult to control the pattern size of the bottom area of the photoresist mask, which effectively determines the area of the tunnel barrier. Moreover, because the surface of the portion where the tunnel barrier is formed is located below that of the surrounding insulating layer, the side surface of this insulating layer is likely to be sputtered during plasma cleaning and plasma oxidation and the sputtered insulating materials attach to and contaminate the surface of the tunnel barrier portion, causing a further problem in addition to the aforementioned problem of the edge step.
A second method is to eliminate the degradation of the pattern accuracy due to the lift-off process using a photoresist mask. After the insulating layer of SiO or SiO.sub.2 is deposited over the substrate with the patterned first superconducting electrode, a hole is opened in the insulating layer by ion etching or reactive sputter etching in accordance with conventional photolithography techniques. Thereafter, the exposed portion of the first supeconducting electrode is oxidized to form the tunnel barrier and the second superconducting electrode is formed thereon.
In this method, too, the surface of the portion for the tunnel barrier is located below that of the surrounding insulating film so that the portion is contaminated by the sputtered insulating materials from the side surface of the insulating layer during plasma cleaning and plasma oxidation. Moreover, the problem of the edge step can not be eliminated.
A third method is to improve the pattern accuracy and contamination resulting from plasma treatment. It is referred to as "SNAP (Selective Niobium Anodization Process)". Refer to H. Kroger, L. N. Smith and D. W. Jillie, "Selective niobium anodization process for fabricating Josephson tunnel junctions", Appl. Phys. Lett., Vol. 39, No. 3, Aug. 1, 1981, pp. 280-282. In accordance with this method, a three-layered film consisting of a lower layer Nb, a tunnel barrier layer and an upper layer Nb is formed and a photoresist is then formed on the portion where a tunnel barrier is to be formed. The upper layer Nb not covered by this photoresist is anodized to form the upper Nb electrode. The photoresist is thereafter removed and a Nb contact layer is formed for the upper Nb electrode.
However, the material that can be used as the electrodes in accordance with this SNAP method is limited and free choice of the material is not possible. In addition, since the volume of the upper layer Nb expands during anodization, an problem of the edge step between the surface of the upper Nb electrode on the tunnel barrier and the surface of the anodized layer remains unsolved.